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general description the max11160 is a 16-bit, 500ksps, sar adc offering excellent ac and dc performance with true unipolar input range, internal reference, and small size. the max11160 measures a +5v (0 to 5v) input range and can operate from a single 5v supply. the max11160 integrates a low drift reference with internal buffer, saving the cost and space of an external reference. this adc achieves 91.7db snr and -103db thd. the max11160 guarantees 16-bit no-missing codes and 1.3 lsb inl (typ). the max11160 communicates using an spi-compatible serial interface at 2.3v, 3v, 3.3v, or 5v logic. the serial interface can be used to daisy-chain multiple adcs for mul - tichannel applications and provides a busy indicator option for simplified system synchronization and timing. the max11160 is offered in a 10-pin, 3mm x 5mm, max m package and is specified over the -40c to +85c temperature range. applications industrial process control data acquisition systems medical instrumentation automatic test equipment beneits and features high dc/ac accuracy improves measurement quality ? 16-bit resolution with no missing codes ? 500ksps throughput rates without pipeline delay/ latency ? 91.7db snr and -103db thd at 10khz ? 0.5 lsb rms transition noise ? 0.5 lsb dnl (typ) and 1.3 lsb inl (typ) highly integrated adc saves cost and space ? 7ppm/c internal reference ? internal reference buffer flexible and low power supply saves space and cost ? +5v analog and +2.3v to +5v digital supply ? 35.4mw power consumption at 500ksps ? 10a in shutdown mode multi-industry standard serial interface and small package reduces size ? spi/qspi?/microwire ? /dsp-compatible ? 3mm x 5mm, tiny 10-pin max package selector guide and ordering information appear at end of data sheet. max is a registered trademark of maxim integrated products, inc. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. 14-bit to 18-bit sar adc family 14-bit 500ksps 16-bit 250ksps 16-bit 500ksps 18-bit 500ksps 5v input internal reference max11167 max11169 max11166 max11168 max11156 max11158 0 to 5v input internal reference max11161 max11165 max11160 max11164 max11150 max11154 0 to 5v input external reference max11262 max11163 max11162 max11152 v ovdd (2.3v to 5v) v dd (5v) ain+ ref host controller 10f 4.7nf max11160 refbuf internal reference gnd 16-bit adc ain- max9632 interface and control cnvst sdo sdi sclk 1f 1f 0 to +5v 10 ? typical operating circuit max11160 16-bit, 500ksps, +5v sar adc with internal reference in max 19-7626; rev 0; 5/15 evaluation kit available downloaded from: http:///
v dd to gnd.............................................................-0.3v to +6v ovdd to gnd........ -0.3v to the lower of (v dd + 0.3v) and +6v ain+ to gnd......................................................................... 7v ain-, ref,to gnd..................-0.3v to the lower of (v dd + 0.3v) and +6v sclk, sdi, sdo, cnvst to gnd............... -0.3v to the lower of (v dd + 0.3v) and +6v maximum current into any pin...........................................50ma continuous power dissipation (t a = +70c) max (derate 8.8mw/c above +70c)......................707mw operating temperature range...........................-40c to +85c junction temperature......................................................+150c storage temperature range............................ -65c to +150c lead temperature (soldering, 10s)..................................+300c soldering temperature (reflow).......................................+260c max junction-to-ambient thermal resistance ( ja )..........113c/w junction-to-case thermal resistance ( jc )................36c/w (note 1) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units analog input (note 3) input voltage range ain+ to ain-, k = 5/4.096 0 +v ref x k v absolute input voltage range ain+ to gnd -0.1 +5.1 v ain- to gnd -0.1 +0.1 input leakage current acquisition phase -10 +0.001 +10 a input capacitance 32 pf input-clamp protection current both inputs -20 +20 ma static performance (note 4) resolution n 16 bits no missing codes 16 bits offset error v ovdd 3.6v -3.25 0.7 +3.25 lsb v ovdd > 3.6v -4.75 +4.75 offset temperature coeficient 0.003 lsb/c gain error v ovdd 3.6v -6.0 +6.0 lsb v ovdd > 3.6v -7.5 +7.5 gain error temperature coeficient 0.007 lsb/c integral nonlinearity inl v ovdd 3.6v -1.75 1.3 +1.75 lsb v ovdd > 3.6v -2.2 +2.2 differential nonlinearity dnl guaranteed by design -1.0 0.5 +1 lsb note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicselectrical characteristics max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 2 downloaded from: http:///
(v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units positive full-scale error v ovdd 3.6v -5.7 2.3 +5.7 lsb v ovdd > 3.6v -7.7 +7.7 analog input cmr cmr referred to the output -1.9 lsb/v power-supply rejection (note 5) psr psr vs. v dd , referred to the output -7.8 lsb/v transition noise 0.5 lsb rms reference ref initial accuracy v ref 4.092 4.096 4.100 v ref temperature coeficient tc ref -17 7 +17 ppm/c ref output impedance z ref 0.1 dynamic performance (note 6) signal-to-noise ratio snr 90.0 91.7 db signal-to-noise plus distortion sinad 89.4 91.4 db spurious-free dynamic range sfdr v ovdd 3.6v 99.5 104.85 db v ovdd > 3.6v 96.5 total harmonic distortion thd v ovdd 3.6v -103.0 -99 db v ovdd > 3.6v -96.5 intermodulation distortion (note 7) imd -115.0 dbfs sampling dynamicsthroughput sample rate 0 500 ksps transient response full-scale step 400 ns full-power bandwidth -3db point 6 mhz -0.1db point > 0.2 aperture delay 2.5 ns aperture jitter 50 ps rms power supplies analog supply voltage v dd 4.75 5.25 v interface supply voltage v ovdd 2.3 5.25 v analog supply current i vdd 5.0 5.6 7.0 ma v dd shutdown current 0.08 10 a interface supply current i ovdd v ovdd = 2.3v 1.44 2.0 ma v ovdd = 5.25v 4.0 5.0 ovdd shutdown current 10 a power dissipation v dd = 5v, v ovdd = 3.3v 35.4 mw electrical characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 3 downloaded from: http:///
(v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units digital inputs (sdi, sclk, cnvst) input voltage high v ih 0.7 x v ovdd v input voltage low v il 0.3 x v ovdd v input hysteresis v hys 0.05 x v ovdd v input capacitance c in 10 pf input current i in v in = 0v or v ovdd -10 +10 a digital output (sdo) output voltage high v oh i source = 2ma v ovdd - 0.4 v output voltage low v ol i sink = 2ma 0.4 v three-state leakage current -10 +10 a three-state output capacitance 15 pf timing (note 8) time between conversions t cyc 2 s conversion time t conv cnvst rising to data available 1.3 1.5 s acquisition time t acq t acq = t cyc - t conv 0.5 s cnvst pulse width t cnvpw cs mode 5 ns sclk period ( cs mode) t sclk v ovdd > 4.5v 14 ns v ovdd > 2.7v 20 v ovdd > 2.3v 25 sclk period (daisy-chain mode) t sclk v ovdd > 4.5v 16 ns v ovdd > 2.7v 24 v ovdd > 2.3v 30 sclk low time t sclkl 6 ns sclk high time t sclkh 6 ns sclk falling edge to data valid delay t dsdo v ovdd > 4.5v 12 ns v ovdd > 2.7v 18 v ovdd > 2.3v 23 electrical characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 4 downloaded from: http:///
note 2: maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25c. limits over the operating temperature range are guaranteed by design and device characterization. note 3: see the analog inputs and overvoltage input clamps sections. note 4: static performance limits are guaranteed by design and device characterization. for definitions, see the definitions section. note 5: defined as the change in positive full-scale code transition caused by a 5% variation in the v dd supply voltage. note 6: 10khz sine wave input, -0.1db below full scale. note 7: f in1 ~ 9.4khz, f in2 ~ 10.7khz, each tone at -6.1db below full scale. note 8: c load = 65pf on sdo. parameter symbol conditions min typ max units cnvst low to sdo d15 msb valid ( cs mode) t en v ovdd > 2.7v 14 ns v ovdd < 2.7v 18 cnvst high or sdi high or last sclk falling edge to sdo high impedance t dis cs mode 20 ns sdi valid setup time from cnvst rising edge t ssdicnv 4-wire cs mode 5 ns sdi valid hold time from cnvst rising edge t hsdicnv 4-wire cs mode 0 ns sclk valid setup time from cnvst rising edge t ssckcnv daisy-chain mode 3 ns sclk valid hold time from cnvst rising edge t hsckcnv daisy-chain mode 3 ns sdi valid setup time from sclk falling edge t ssdisck v ovdd > 4.5v, daisy-chain mode 3 ns v ovdd > 2.7v, daisy-chain mode 5 v ovdd > 2.3v, daisy-chain mode 6 sdi valid hold time from sclk falling edge t hsdisck daisy-chain mode 0 ns sdi high to sdo high t dsdosdi daisy-chain mode with busy indicator, v ovdd > 4.5v 10 ns daisy-chain mode with busy indicator, v ovdd > 2.7v 15 daisy-chain mode with busy indicator, v ovdd > 2.3v 20 (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) electrical characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 5 downloaded from: http:///
(v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; t a = +25 n c, unless otherwise noted.) -6 -4 -2 0 2 4 6 4.75 4.85 4.95 5.05 5.15 5.25 error (lsb) v dd (v) offset error gain error offset and gain error vs. v dd supply voltage average of 128 devices toc02 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 8192 16384 24576 32768 40960 49152 57344 65536 inl (lsb) output code (decimal) integral nonlinearity vs. code single device toc04 -6 -4 -2 0 2 4 6 -40 -15 10 35 60 85 inl (lsb) temperature ( c) inl vs. temperature max inl min inl average of 128 devices toc06 -6 -4 -2 0 2 4 6 -40 -15 10 35 60 85 error (lsb) temperature ( c) offset error gain error offset and gain error vs. temperature average of 128 devices toc01 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 8192 16384 24576 32768 40960 49152 57344 65536 dnl (lsb) output code (decimal) differential nonlinearity vs. code single device toc03 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85 dnl (lsb) temperature ( c) dnl vs. temperature max dnl min dnl average of 128 devices toc05 typical operating characteristics max11160 16-bit, 500ksps, +5v sar adc with internal reference in max maxim integrated 6 www.maximintegrated.com downloaded from: http:///
(v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; t a = +25 n c, unless otherwise noted.) -6 -4 -2 0 2 4 6 4.75 4.85 4.95 5.05 5.15 5.25 inl (lsb) v dd (v) inl vs. v dd supply voltage max inl min inl average of 128 devices toc08 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 4.75 4.85 4.95 5.05 5.15 5.25 dnl (lsb) v dd (v) dnl vs. v dd supply voltage max dnl average of 128 devices toc07 0 20000 40000 60000 80000 100000 32763 32765 32767 32769 32771 32773 number of occurrences output code (decimal) output noise histogram no average single device stdev = 0.55 lsb toc09 0 40000 80000 32763 32765 32767 32769 32771 32773 number of occurrences output code (decimal) output noise histogram with 4- sample average single device stedv = 0.23 lsb toc10 4.090 4.092 4.094 4.096 4.098 4.100 4.102 4.104 -40 -15 10 35 60 85 v ref (v) temperature ( c) internal reference voltage (ref pin) vs. temperature 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 15 devices toc11 0 10 20 30 40 50 60 4.0990 4.0985 4.0980 4.0975 4.0970 4.0965 4.0960 4.0955 4.0950 4.0945 4.0940 4.0935 4.0930 number of occurrences ref pin voltage (v) initial error voltage on ref pin 303 devices mean = 4096.0mv stdev = 1.2mv stdev = 282ppm toc12 typical operating characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max maxim integrated 7 www.maximintegrated.com downloaded from: http:///
(v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; t a = +25 n c, unless otherwise noted.) 80 85 90 95 100 105 110 115 0.1 1.0 10.0 100.0 sfdr and - thd (db) frequency (khz) sfdr and - thd vs. frequency sfdr thd v in = - 0.1dbfs average of 128 devices toc18 14.0 14.5 15.0 15.5 16.0 86 88 90 92 94 96 98 0.1 1.0 10.0 100.0 enob (bits) sinad (db) frequency (khz) sinad and enob vs. frequency sinad enob v in = - 0.1dbfs average of 128 devices toc17 4.0955 4.0956 4.0957 4.0958 4.0959 4.0960 4.0961 4.0962 4.0963 4.0964 4.0965 4.75 4.85 4.95 5.05 5.15 5.25 v ref (v) v dd (v) internal reference voltages vs. v dd voltage ref average of 200 devices toc14 -140 -120 -100 -80 -60 -40 -20 0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 magnitude (db) frequency (khz) two tones imd n sample = 16384 f in1 = 9674hz v in1 = - 6.1dbfs f in2 = 10101hz v in2 = - 6.1dbfs single device imd = - 117dbfs toc16 -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 magnitude (db) frequency (khz) fft plot n sample = 4096 f in = 10132hz v in = - 0.1dbfs single device snr = 91.8db sinad = 91.54db thd = - 105.0db sfdr = 107.5db toc15 0 10 20 30 40 50 60 70 12 10 86420 -2 -4 -6 -8 -10 -12 -14 -16 number of occurrences thermal drift (ppm/ c) 25c to -40c 25c to +85c ref pin thermal drift slope 303 devices mean = 2.1ppm/ c stdev = 1.9ppm/ c 303 devices mean = - 7.3ppm/ c stdev = 1.9ppm/ c toc13 typical operating characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max maxim integrated 8 www.maximintegrated.com downloaded from: http:///
(v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; t a = +25 n c, unless otherwise noted.) 85 90 95 100 105 110 115 -40 -15 10 35 60 85 sfdr and - thd (db) temperature ( c) thd sfdr sfdr and thd vs. temperature f in = 10khz v in = - 0.1dbfs average of 128 devices toc20 95 97 99 101 103 105 107 109 111 113 115 4.75 4.85 4.95 5.05 5.15 5.25 sfdr and - thd (db) v dd (v) thd sfdr thd and sfdr vs. v dd supply voltage f in = 10khz v in = - 0.1dbfs average of 128 devices toc22 86 88 90 92 94 96 98 -40 -15 10 35 60 85 snr and sinad (db) temperature ( c) snr sinad snr and sinad vs. temperature f in = 10khz v in = - 0.1dbfs average of 128 devices toc19 86 88 90 92 94 96 98 4.75 4.85 4.95 5.05 5.15 5.25 snr and sinad (db) v dd (v) snr sinad snr and sinad vs. v dd supply voltage f in = 10khz v in = - 0.1dbfs average of 128 devices toc21 -90 -80 -70 -60 -50 -40 -30 0.1 1.0 10.0 100.0 1000.0 cmr (db) frequency (khz) cmr vs. input frequency v ain+ = v ain - = 100mv single device toc23 -80 -70 -60 -50 -40 -30 -20 0.1 1.0 10.0 100.0 1000.0 psr (db) frequency (khz) psr vs. v dd supply frequency v vdd = 5.0 250mv v ovdd = 3.3v single device toc24 typical operating characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max maxim integrated 9 www.maximintegrated.com downloaded from: http:///
(v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; t a = +25 n c, unless otherwise noted.) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -15 10 35 60 85 i ovdd (ma) temperature ( c) ovdd supply current vs. temperature 500ksps 10ksps c sdo = 65pf average of 128 devices toc26 5.0 5.2 5.4 5.6 5.8 6.0 -40 -15 10 35 60 85 i vdd (ma) temperature ( c) v dd supply current vs. temperature average of 128 devices toc25 0 1 2 3 4 5 6 2.25 2.75 3.25 3.75 4.25 4.75 5.25 i ovdd (ma) v ovdd (v) ovdd supply current vs. ovdd supply voltage 500ksps 10ksps c sdo = 65pf average of 128 devices toc28 5.0 5.4 5.8 6.2 6.6 7.0 4.75 4.85 4.95 5.05 5.15 5.25 i vdd (ma) v dd (v) v dd supply current vs. v dd supply voltage average of 128 devices toc27 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 shutdown current (a) v dd or v ovdd (v) v dd and ovdd shutdown current vs. supply voltage ivdd iovdd average of 128 devices toc30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -40 -15 10 35 60 85 shutdown current (a) temperature ( c ) v dd and ovdd shutdown current vs. temperature ivdd iovdd average of 128 devices toc29 typical operating characteristics (continued) max11160 16-bit, 500ksps, +5v sar adc with internal reference in max maxim integrated 10 www.maximintegrated.com downloaded from: http:///
pin name function 1 ref internal reference bypass. bypass to gnd in close proximity with a x5r or x7r 10f 16v capacitor. se e the layout, grounding, and bypassing section. 2 v dd analog power supply. bypass v dd to gnd with a 0.1f capacitor as close as possible to each device and one 10f capacitor per board. 3 ain+ positive analog input 4 ain- negative analog input. connect ain- to the analog ground plane or to a remote sense ground. 5 gnd power-supply ground 6 cnvst conversion start input. the rising edge of cnvst initiates the conversions and selects the interface mode: daisy-chain or cs . in cs mode, either sdi or cnvst can enable the serial output signals when low. if sdi or cnvst is low when the conversion is completed, the busy indicator feature is enabled. 7 sdo serial data output. sdo transitions on the falling edge of sclk. 8 sclk serial clock input. clocks data out of the serial interface when the device is selected. 9 sdi serial data input and mode select input. daisy-chain mode is selected if sdi is low during the cnvst rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. cs mode is selected if sdi is high during the cnvst rising edge. in this mode, either sdi or cnvst can enable the serial output signals when low. if sdi or cnvst is low when the conversion is completed, the busy indicator feature is enabled. 10 ovdd digital power supply. ovdd can range from 2.3v to v dd . bypass ovdd to gnd with a 0.1f capacitor for each device and one 10f per board. 10 23 4 5 98 7 6 cnvst sdo sclk sdi max top view + 1 ovdd max11160 ref v dd ain+ ain- gnd pin description pin coniguration max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 11 downloaded from: http:///
detailed description the max11160 is a 16-bit single-channel, pseudo-differ - ential adc with maximum throughput rates of 500ksps. both inputs (ain+ and ain-) are sampled with a pseudo- differential on-chip track-and-hold. this adc includes a precision internal reference that allows for measuring an input voltage interval from 0 to 5v. the max11160 inputs are protected for up to q 20ma of overrange current. this adc is powered from a 4.75v to 5.25v analog supply (v dd ) and a separate 2.3v to 5.25v digital supply (ovdd). the max11160 requires 500ns to acquire the input sample on an internal track-and-hold and then converts the sampled signal to 16 bits of resolu - tion using an internally clocked converter. analog inputs the max11160 adc consists of a true sampling pseudo- differential input stage with high-impedance, capacitive inputs. the internal t/h circuitry features a small-signal bandwidth of about 6mhz to provide 16-bit accurate sampling in 500ns. this allows for accurate sampling of a number of scanned channels through an external multiplexer. the max11160 accurately converts input signals on the ain+ input in the interval from ain- to (+5v + ain-). ain+ has a max input interval from -0.1v to +5.1v. ain- has a max input interval from -0.1v to +0.1v. the max11160 performs a true differential sampling on inputs between ain+ and ain- with good common-mode rejection (see the typical operating circuit ). this allows for improved sampling of remote transducer inputs. the max11160 includes a patented input switch archi - tecture that allows direct sampling of high-impedance sources. 16-bit adc ain+ ain- max11160 interface and control ref sdisclk sdo cnvst ovdd ref internal reference refbuf v dd gnd functional diagram max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 12 downloaded from: http:///
overvoltage input clamps the max11160 includes an input clamping circuit that activates when the input voltage at ain+ is above (v dd + 300mv) or below -300mv. the clamp circuit remains high impedance while the input signal is within the range of +(v dd + 100mv) and -100mv and draws little to no cur - rent. however, when the input signal exceeds this range the clamps begin to turn on. consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of -100mv to +(v dd + 100mv). to make use of the input clamps, connect a resistor (r s ) between the ain+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed q 20ma. note that the voltage at the ain+ input pin limits to approximately 7v during a fault condition so the following equation can be used to calculate the value of r s : max fault s v 7v r 20ma ? = where v fault max is the maximum voltage that the source produces during a fault condition. figure 1 and figure 2 illustrate the clamp circuit volt - age current characteristics for a source impedance r s = 1170 i . while the input voltage is within the (-300mv to (v dd + 300mv) range, no current flows in the input clamps. once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. reference the max11160 includes a precision internal reference source as well as an internal reference buffer circuit to drive the converter. the internal reference buffer requires a low inductance and esr external decoupling capacitor of at least 10f to be placed as close as possible to the reference pin. input ampliier the conversion results are accurate when the adc acquires the input signal for an interval longer than the input signal's worst-case settling time. the adc input sampling capacitor charges during the acquisition period. during this acquisition period, the settling of the sampled voltage is affected by the source resistance and the input sampling capacitance. sampling error can be estimated by modeling the time constant of the total input capaci - tance and the driving source impedance. figure 1. input clamp characteristics figure 2. input clamp characteristics (zoom in) max11160 input clamp characteristics voltage at ain+ pin and input source (v) current into pin (ma) 30 20 10 -10 0 -20 -15 -5 5 15 25 -25 -30 40 r s = 1170 i v dd = 5.0v ain+ pin input source max11160 input clamp characteristics voltage at ain+ pin and input source (v) current into pin (ma) 6 8 4 0 -2 2 -15 -5 5 15 25 -25 -4 10 ain+ pin input source r s = 1170 i v dd = 5.0v max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 13 downloaded from: http:///
although the max11160 is easy to drive, an amplifier buffer is recommended if the source impedance is such that when driving a switch capacitor of ~32pf a settling error in the desired sampling period will occur. if this is the case, it is recommended that a configuration shown in the typical operating circuit be used where at least a 2nf capacitor is attached to the ain+ pin. this capacitance reduces the size of the transient at the start of the acquisi - tion period, which will generate an input signal dependent offset error in some buffers. regardless of whether an external buffer amp is used or not, the time constant, r source c load , of the input should not exceed t acq /12, where r source is the total signal source impedance, c load is the total capacitance at the adc input (external and internal) and t acq is the acquisition period. thus to obtain accurate sampling in a 0.5 s acquisition time a source impedance of less than 1k should be used if driving the adc directly. when driving the adc from a buffer, it is recommended a series resistance (5 to 50 typical) between the amplifier and the external input capacitance as shown in the typical operating circuit . these amplifier features help to select the adc driver: 1) fast settling time: for multichannel multiplexed appli - cations the driving operational amplifier must be able to settle to 16-bit resolution when a full-scale step is applied during the minimum acquisition time. 2) low noise: it is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. in the case of the max11160, settling in a 0.5s duration requires a rc filter bandwidth of approximately 4mhz. with this bandwidth, it is preferable to use an amplifier that will produce an output noise spectral density of less than 4.5nv/ hz , to ensure that the overall snr is not degraded significantly. it is recommended to insert an external rc filter at the max11160 ain+ input to attenuate out-of-band input noise and preserve the adcs snr. the effective rms noise at the max11160 ain+ input is 40 f v, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum snr performance. 3) thd performance: the input buffer amplifier used should have better thd performance than the max11160 to ensure the thd of the digitized signal is not degraded. table 1 summarizes the operational amplifiers that are compatible with the max11160. the max9632 has suf - ficient bandwidth, low enough noise and distortion to sup - port the full performance of the max11160. the max9633 is a dual amp and can support buffering for true pseudo- differential sampling. table 1. list of recommended adc driver op amps for max11160 amplifier input-noise density (nv/ hz ) small-signal bandwidth (mhz) slew rate (v/s) thd (db) i cc (ma) comments max9632 0.9 55 30 -128 3.9 low noise, thd at 10khz max9633 3 27 18 -130 3.5/amp low noise, dual amp, thd at 10khz max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 14 downloaded from: http:///
transfer function the ideal transfer characteristic for the max11160 is shown in figure 3 . the precise location of various points on the transfer function are given in table 2 . digital interface the max11160 includes three digital inputs (cnvst, sclk, and sdi) and a single digital output (sdo). the adc can be configured for one of six interface modes, allowing the device to support a wide variety of application needs. the 3-wire and 4-wire cs interface modes are compat - ible with spi, qspi, digital hosts, and dsps. the 3-wire interface uses cnvst, sclk, and sdo for minimal wiring complexity and is ideally suited for isolated applications. the 4-wire interface allows cnvst to be independent of output data readback (sdi) affording the highest level of individual device control. this configuration is useful for low jitter or multichannel, simultaneously sampled applications. the 3-wire daisy-chain mode is the easiest way to config - ure a multichannel, simultaneous-sampling system. this system is built by cascading multiple adcs into a shift register structure. the cnvst and sclk inputs are com - mon to all adcs, while the sdo output of one device feeds the sdi input of the next device in the chain. the 3-wire interface is simply the cnvst, sclk, and sdo of the last adc in the chain. the selection of cs or daisy-chain modes is controlled by the sdi logic level during the rising edge of cnvst. the cs mode is selected if sdi is high and the daisy-chain mode is selected if sdi is low. if sdi and cnvst are con - nected together, the daisy-chain mode is selected. in each of the three modes described above (3-wire cs mode, 4-wire cs mode, and daisy-chain mode), the user must externally time out the maximum adc conver - sion time before commencing readback. alternatively, the max11160 offers a busy indicator feature on sdo in each mode to eliminate external timer circuits. when busy indication is enabled, sdo provides a busy indicator bit to signal the end of conversion. one additiona l sclk is required to flush the sdo busy indication bit prior t o reading back the data. busy indicator is enabled in cs mode if cnvst or sdi is low when the adc conversion completes. in daisy-chain mode, the busy indicator is selected based on the state of sclk at the rising edge of cnvst. if sclk is high, the busy indicator is enabled; otherwise, the busy indicator is not enabled. the following sections provide specifics for each of the six serial interface modes. due to the possibility of perfor - mance degradation, digital activity should only occur after conversion is completed or limited to the first half of the conversion phase. having sclk or sdi transitions near the sampling instant can also corrupt the input sample accuracy. therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of cnvst. these times are denoted as t ssckcnv and t hsckcnv in all subsequent timing diagrams. in all interface modes, the data on sdo is valid on both sclk edges. however, input setup time into the receiving host will be maximized when data is clocked into that host on the falling sclk edge. doing so will allow for higher data transfer rates between the max11160 and the receiv - ing host and consequently higher converter throughput. figure 3. unipolar transfer function table 2. transfer function example code transition unipolar input (v) digital output code (hex) +fs - 1.5 lsb +4.999886 fffe - ffff midscale + 0.5 lsb 2.500038 8000 - 8001 midscale 2.500000 8000 midscale - 0.5 lsb 2.499962 7fff - 8000 + 0.5 lsb 0.000038 0000 - 0001 input voltage (lsb) transition +fs - 1.5 lsb 0.5 lsb output code (hex) 7ffe 00001 00000 8000 7fff 8001 0 +fs 4.096 +5 v ref +fs = ffff fffe 65536 +fs-0 lsb = +fs C 1 lsb fs/2 max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 15 downloaded from: http:///
shutdown in all interface modes, the max11160 can be placed into a shutdown state by holding sclk high while pulling cnvst from high to low. supply current is reduced to less than 10a on both v dd and ovdd supplies (see figure 4 ). to wake up from shutdown mode, hold sclk low and pull cnvst from high to low. adc modes of operation the max11160 six modes of operation are summarized in table 3 . for each of the six modes of operation a typical application model and list of benefits are described. figure 4. entering and exiting shutdown mode table 3. adc modes of operation mode typical application and benefits cs mode 3-wire, no-busy indicator single adc connected to spi-compatible digital host. minimal wiring complexity; ideally suited for isolated applications. cs mode 3-wire, with busy indicator single adc connected to spi-compatible digital host with interrupt input. minimal wiring complexity; ideally suited for isolated applications. cs mode 4-wire, no-busy indicator multiple adcs connected to spi-compatible digital host. cnvst used for acquisition and conversion; ideally suited for low jitter applications and simul t aneous sampling. sdi used to control data readback. cs mode 4-wire, with busy indicator single adc connected to spi-compatible digital host with interrupt input. cnvst used for acquisition and conversion; ideally suited for low jitter applications. daisy-chain mode, no-busy indicator multiple adcs connected to 3-wire serial interface. minimal wiring complexity; ideally suited for multichannel simultaneous sampled isolated applications. daisy-chain mode, with busy indicator multiple adcs connected to 3-wire serial interface with busy indicator. minimal wiring complexity; ideally suited for multichannel simultaneous sampled isolated applications. cnvst t hsclkcnv sclk t ssclkcnv t ssclkcnv t hsclkcnv internal shutdown signal powered down powered up max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 16 downloaded from: http:///
cs mode 3-wire, no-busy indicator the 3-wire cs mode with no-busy indicator is ideally suited for isolated applications that require minimal wiring complexity. in figure 5 , a single adc is connected to an spi-compatible digital host with corresponding timing given in figure 6 . with sdi connected to ovdd, a rising edge on cnvst completes the acquisition, initiates the conversion and forces sdo to high impedance. the conversion continues to completion irrespective of the state of cnvst, allowing cnvst to be used as a select line for other devices on the board. cnvst must be returned high before the minimum conversion time and held high until the maximum conver - sion time to avoid generating the busy signal indicator. when the conversion is complete, the max11160 enters the acquisition phase. drive cnvst low to output the msb onto sdo. the remaining data bits are then clocked by subsequent sclk falling edges. sdo returns to high impedance after the 16th sclk falling edge or when cnvst goes high. figure 6. cs mode 3-wire, no-busy indicator serial interface timing (sdi high) figure 5. cs mode 3-wire, no-busy indicator connection diagram (sdi high) 1 2 3 14 15 16 t conv conversion acquisition d15 d14 d13 d1 d0 t sclkl t sclkh t en t dis t dsdo t sclk t ssckcnv t hsckcnv sdo cnvst acquisition sclk t cnvpw t cyc t acq sdo max11160 sdi sclk clk data in digital host cnvst ovdd convert max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 17 downloaded from: http:///
cs mode 3-wire, with busy indicator the 3-wire cs mode with busy indicator is shown in figure 7 where a single adc is connected to an spi-compatible digital host with interrupt input. the corresponding timing is given in figure 8 . with sdi connected to ovdd, a rising edge on cnvst completes the acquisition, initiates the conversion and forces sdo to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. cnvst must be returned low before the minimum conversion time and held low until the busy signal is gen - erated. when the conversion is complete, sdo transitions from high impedance to a low logic level signaling to the digital host through the interrupt input that data readback can commence. the max11160 then enters the acquisition phase. the data bits are clocked out, msb first, by subse - quent sclk falling edges. sdo returns to high impedance after the 17th sclk falling edge or when cnvst goes high and is then pulled to ovdd through the external pullup resistor. figure 7. cs mode 3-wire with busy indicator connection diagram (sdi high) figure 8. cs mode 3-wire with busy indicator serial interface timing (sdi high) sdo sdi sclk clk data in digital host cnvst ovdd convert 10k ? ovdd irq max11160 sdo 1 2 3 15 16 17 cnvst t conv conversion acquisition acquisition t cyc busy bit d14 d13 d1 d0 t sclkl t sclkh t dis t dsdo sclk t sclk 4 d15 t cnvpw t hsckcnv t ssckcnv t acq max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 18 downloaded from: http:///
cs mode 4-wire, no-busy indicator the 4-wire cs mode with no-busy indicator is ideally suited for multichannel applications. in this case, the cnvst pin may be used for low-jitter simultaneous sampling while the sdi pin(s) are used to control data readback. in figure 9 , two adcs are connected to an spi-compatible digital host with corresponding timing given in figure 10 . with sdi high, a rising edge on cnvst completes the acquisition, initiates the conversion, and forces sdo to high impedance. this mode requires cnvst to be held high during the conversion and data readback phases. note that if cnvst and sdi are low, sdo is driven low. during the conversion, the sdi pin(s) can be used as a select line for other devices on the board, but must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid gen - erating the busy signal indicator. when the conversion is complete, the max11160 enters the acquisition phase. adc data is read by driving its respective sdi line low, outputting the msb onto sdo. the remaining data bits are then clocked by subsequent sclk falling edges. sdo returns to high impedance after the 16th sclk falling edge or when cnvst goes high. figure 9. cs mode 4-wire, no-busy indicator connection diagram figure 10. cs mode 4-wire, no-busy indicator serial interface timing sdo sdi sclk clk data in digital host cnvst convert cs1 cs2 sdo sdi sclk cnvst max11160 max11160 t ssdicnv t hsdicnv sdi(cs1) sdi(cs2) 1 2 3 15 16 t conv conversion acquisition d15 d14 d13 d1 d0 t sclkl t sclkh t en t dis t dsdo t sclk sdo cnvst acquisition sclk d15 d14 d1 d0 32 17 18 31 t cyc t en d13 19 t dis t acq t cnvpw t cnvpw t hsckcnv t ssckcnv max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 19 downloaded from: http:///
cs mode 4-wire, with busy indicator the 4-wire cs mode with busy indicator is shown in figure 11 where a single adc is connected to an spi-compatible digital host with interrupt input. the corresponding timing is given in figure 12 . this mode is ideally suited for single adc applications where the cnvst pin may be used for low-jitter sampling while the sdi pin is used for data read - back. with sdi high, a rising edge on cnvst completes the acquisition, initiates the conversion and forces sdo to high impedance. this mode requires cnvst to be held high during the conversion and data readback phases. note that if cnvst and sdi are low, sdo is driven low. during the conversion, the sdi pin can be used as a select line for other devices on the board, but must be returned low before the minimum conversion time and held low until the busy signal is generated. when the conversion is complete sdo transitions from high impedance to a low logic level signaling to the digital host through the interrupt input that data readback can commence. the max11160 then enters the acquisition phase. the data bits are clocked out, msb first, by subse - quent sclk falling edges. sdo returns to high impedance after the 17th sclk falling edge or when cnvst goes high and is then pulled to ovdd through the external pullup resistor. figure 11. cs mode 4-wire with busy indicator connection diagram figure 12. cs mode 4-wire with busy indicator serial interface timing sdo sdi sclk clk data in digital host cnvst convert 10k ? ovdd irq cs1 max11160 sclk sdo 1 2 3 15 16 17 cnvst t conv conversion acquisition acquisition d15 d14 d1 d0 t sclk t sclkl t sclkh t dis t dsdo t ssdicnv t hsdicnv sdi t acq busy bit t cnvpw t hsckcnv t ssckcnv t cyc max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 20 downloaded from: http:///
daisy-chain mode, no-busy indicatorthe daisy-chain mode with no-busy indicator is ideally suit - ed for multichannel isolated applications that require mini - mal wiring complexity. simultaneous sampling of multiple adc channels is realized on a 3-wire serial interface where data readback is analogous to clocking a shift register. in figure 13 , two adcs are connected to an spi-compatible digital host with corresponding timing given in figure 14 . the daisy-chain mode is engaged when the max11160 detects the low state on sdi at the rising edge of cnvst. in this mode, cnvst is brought low and then high to trigger the completion of the acquisition phase and the start of a conversion. a low sclk state on the rising edge of cnvst signals to the internal controller that the no-busy indicator will be output. when in chain mode, the sdo output is driven active at all times. when sdi and cnvst are both low, sdo is driven low, thus engaging the daisy-chain mode of operations on the downstream max11160 parts. for example, in figure 13 part a has its sdi tied low so the chain mode of operation will be selected on every conversion. when cnvst goes low to trigger another conversion, part as sdo and con - sequently part bs sdi go low as well. on the next cnvst rising edge both parts a and b will select the daisy-chain mode interface. when a conversion is complete, the msb is presented onto sdo, and the max11160 returns to the acquisition phase. the remaining data bits, stored within the internal shift register, are clocked out on each subsequent sclk falling edge. the sdi input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. each adc in the chain outputs its msb data first requiring 16 n clocks to read back n adcs. in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 6ns digital host setup time and 3v interface, up to four max11160 devices running at a conversion rate of 436ksps can be daisy-chained on a 3-wire port. figure 13. daisy-chain mode, no-busy indicator connection diagram figure 14. daisy-chain mode, no-busy indicator serial interface timing sdo sdi sclk clk data in digital host cnvst convert sdo sdi sclk cnvst max11160 max11160 device a device b sdoa sdob d a 15 sclk sdo a = sdi b 1 2 3 14 15 16 cnvst t conv conversion acquisition acquisition d a 14 d a 13 d a 1 d a 0 t sclkl t sclkh t dsdo 30 31 32 17 18 t hsckcnv t ssckcnv sdo b d b 15 d b 14 d b 13 d b 1 d b 0 d a 15 d a 14 d a 1 d a 0 t ssdisck t hsdisck t cnvpw select no busy output select chain mode t cyc t acq t sclk max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 21 downloaded from: http:///
daisy-chain mode, with busy indicator the daisy-chain mode with busy indicator is shown in figure 15 where three adcs are connected to an spi- compatible digital host with corresponding timing given in figure 16 . the daisy-chain mode is engaged when the max11160 detects a low state on sdi at the rising edge of cnvst. additionally, sdi can be tied directly to cnvst to trigger the chain interface mode. in this mode, cnvst is brought low and then high to trigger the completion of the acquisi - tion phase and the start of a conversion. a high sclk state on the rising edge of cnvst signals to the internal control - ler that the busy indicator will be outputted. when in daisy-chain mode, the sdo output is driven active at all times. when sdi and cnvst are both low, sdo is driven low, thus engaging the daisy-chain mode of operations on the downstream max11160 parts. for example, in figure 15 part a has its sdi tied low so the daisy-chain mode of oper - ation will be selected on every conversion. when cnvst goes low to trigger another conversion, part as sdo and consequently part bs sdi go low as well. the same is true on part cs sdi input. consequently, on the next cnvst rising edge all parts in the chain will select the daisy-chain mode interface. when a conversion is complete, the busy indicator is pre - sented onto each sdo, and the max11160 returns to the acquisition phase. as each part completes its conversion, it looks for a busy enable signal on its sdi pin from the earlier part in the chain. when it sees a busy enable signal on its input and its own conversion has completed, it enables its busy output signal on sdo. thus the busy enable signals are propagated down the chain and the final busy enable signal at the host indicates that all devices in the chain have completed their conversion and all can be readout. figure 15. daisy-chain mode with busy indicator connection diagram figure 16. daisy-chain mode with busy indicator serial interface timing sdo sdi sclk clk data in digital host cnvst convert sdo sdi sclk cnvst sdo sdi sclk cnvst irq max11160 max11160 max11160 device a device b device c sdo c sdo a sdo b sdo a = sdi b 1 2 3 16 17 cnvst = sdi a t conv conversion acquisition acquisition d a 15 d a 14 d a 13 d a 1 d a 0 t sclkh t sclkl t dsdo 18 19 t ssdisck t hsdisck 4 15 32 33 34 35 31 48 49 47 sdo b = sdi c d b 15 d b 14 d b 13 d b 1 d b 0 d a 15 d a 14 d a 1 d a 0 sdo c d c 15 d c 14 d c 13 d c 1 d c 0 d b 15 d b 14 d b 1 d b 0 d a 15 d a 14 d a 1 d a 0 sclk t hsckcnv t ssckcnv busy bit t cnvpw select busy mode select chain mode select chain mode t dsdosdi t dsdosdi t dsdosdi t dsdosdi t dsdosdi t cyc t acq t sclk busy bit busy bit max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 22 downloaded from: http:///
the conversion data bits are stored within the internal shift register and clocked out on each subsequent sclk falling edge. the sdi input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. with busy indicator mode selected, the busy bit from each part is not chained on the first falling sclk edge in the readout pattern. consequently, the number of falling sclks needed to read back all data from n adcs is 16 n + 1 falling edges. in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 6ns digital host setup time and 3v interface, up to four max11160 devices running at a conversion rate of 434ksps can be daisy-chained on a 3-wire port. layout, grounding, and bypassing for best performance, use pcbs with ground planes. ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines paral - lel to one another (especially clock lines), and avoid run - ning digital lines underneath the adc package. a single solid gnd plane configuration with digital signals routed from one direction and analog signals from the other pro - vides the best performance. connect the gnd pin on the max11160 to this ground plane. keep the ground return to the power supply low impedance and as short as possible for noise-free operation. a 4.7nf c0g (or npo) ceramic chip capacitor should be placed between ain+ and the ground plane as close as possible to the max11160. this capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. if ain- is to be used for remote sense, put a matching 4.7nf c0g ceramic capacitor as close to this pin as well to mini - mize the effect to the inductance in the remote sense line. for best performance, decouple the ref output to the ground plane with a 16v, 10f or larger ceramic chip capacitor with a x5r or x7r dielectric in a 1210 or smaller case size. ensure that all bypass capacitors are connect - ed directly into the ground plane with an independent via. bypass v dd and ovdd to the ground plane with 0.1 f f ceramic chip capacitors on each pin as close as pos - sible to the device to minimize parasitic inductance. add at least one bulk 10 f f decoupling capacitor to v dd and ovdd per pcb. for best performance, bring a v dd power plane in on the analog interface side of the max11160 and a ovdd power plane from the digital interface side of the device. deinitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. offset error for the max11160, the offset error is defined at code center 0x0000. this code center should occur at 0v input between ain+ and ain-. the offset error is the actual volt - age required to produce code center 0x0000, expressed in lsb. gain error gain error is defined as the difference between the actual change in analog input voltage required to produce a top code transition minus a bottom code transition, and the ideal change in analog input voltage range to produce the same code transitions. it is expressed in lsb. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full- scale analog input power to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quantiza - tion noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the power signal to the power noise, which includes all spectral components not including the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys power to the power of all the other adc output signals: max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 23 downloaded from: http:///
rms rms signal sinad(db) 20 log (noise distortion) ???? = + ???? effective number of bits the effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantiza - tion noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: sinad 1.76 enob 6.02 ? = total harmonic distortion total harmonic distortion (thd) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. this is expressed as: 2345 1 pppp thd 10 log p +++ ???? = ???? where p 1 is the fundamental power and p 2 through p 5 is the power of the 2nd- through 5th-order harmonics.spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the power of the fundamental (maximum signal component) to the power of the next-largest frequency component. aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitteraperture jitter (t aj ) is the sample-to-sample variation in aperture delay. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in a manner that ensures that the signals slew rate does not limit the adcs performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full-power input bandwidth frequency. max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 24 downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. package type package code outline no. land pattern no. 10 max u10+2 21-0061 90-0330 part temp range pin-package max11160eub+ -40c to +85c 10 max max11160eub+t -40c to +85c 10 max part bits input range (v) reference package speed (ksps) max11262 14 0 to 5 external 3mm x 5mm max-10 500 max11160 16 0 to 5 internal 3mm x 5mm max-10 500 max11161 16 0 to 5 internal 3mm x 5mm max-10 250 max11162 16 0 to 5 external 3mm x 5mm max-10 500 max11163 16 0 to 5 external 3mm x 5mm max-10 250 max11164 16 0 to 5 internal/external 3mm x 3mm tdfn-12 500 max11165 16 0 to 5 internal/external 3mm x 3mm tdfn-12 250 max11166 16 5 internal/external 3mm x 3mm tdfn-12 500 max11167 16 5 internal/external 3mm x 3mm tdfn-12 250 max11168 16 5 internal 3mm x 5mm max-10 500 max11169 16 5 internal 3mm x 5mm max-10 250 max11150 18 0 to 5 internal 3mm x 5mm max-10 500 max11152 18 0 to 5 external 3mm x 5mm max-10 500 max11154 18 0 to 5 internal/external 3mm x 3mm tdfn-12 500 max11156 18 5 internal/external 3mm x 3mm tdfn-12 500 max11158 18 5 internal 3mm x 5mm max-10 500 selector guide ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix char - acter, but the drawing pertains to the package regardless of rohs status. max11160 16-bit, 500ksps, +5v sar adc with internal reference in max www.maximintegrated.com maxim integrated 25 downloaded from: http:///
revision number revision date description pages changed 0 5/15 initial release revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max11160 16-bit, 500ksps, +5v sar adc with internal reference in max ? 2015 maxim integrated products, inc. 26 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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